1. Field of the Invention
The present invention relates to a power supply voltage detecting circuit constituted by MIS transistors.
2. Description of the Related Art
Up to now, in the case where a power supply voltage supplied in a semiconductor integrated circuit is low and a circuit operation is apt to become unstable, a circuit has been reset at the time of a low power supply voltage by using a power supply voltage detecting circuit as shown in FIG. 10.
Hereinafter, the circuit will be described on the basis of the drawings.
An N-type depletion MIS transistor 2003 in which a gate electrode and a source electrode are connected to ground and which operates as a constant current element, is connected to an input side of a current mirror circuit constituted by a P-type enhancement MIS transistor 2001 and a P-type enhancement MIS transistor 2002, and an N-type enhancement MIS transistor 2004 is connected to an output side node N3 of the current mirror circuit.
Besides, the circuit includes an N-type enhancement MIS transistor 2008 in which both a drain electrode and a gate electrode are saturation-connected to Vcc, and an N-type depletion MIS transistor 2007 in which a drain electrode is connected to a source electrode of the N-type enhancement MIS transistor 2008, and a gate electrode and a source electrode are connected to ground, and which operates as a constant current element, a connection point N2 between the N-type enhancement MIS transistor 2008 and the N-type depletion MIS transistor 2007 is connected to a gate electrode of the N-type enhancement MIS transistor 2004, and a change in potential at the connection point N2 is amplified and appears at the node N3.
The N-type enhancement MIS transistor 2008 and the N-type depletion MIS transistor 2007 constitute a bias circuit 2009, a potential at the node N3 is further amplified by an inverter constituted by a P-type enhancement MIS transistor 2005 and an N-type enhancement MIS transistor, its waveform is shaped, and it is outputted as VDETX as a detection output of the power supply voltage.
FIGS. 11A and 11B show potential changes at respective nodes N1, N2 and N3 with respect to a change of the power supply voltage, and although the node N3 outputs a potential almost equal to the power supply voltage in a detection state of a low voltage, in the state where the low voltage is released, an output is not accurately lowered to the grand level, and as the power supply voltage becomes high, it gradually approaches the ground level.
This is because immediately after detection release of the potential at the node N2, the gate electrode of the N-type enhancement MIS transistor 2004 can not be sufficiently biased, and the current drive capability of the N-type enhancement MIS transistor 2004 can not sufficiently overcome the current supply capability of the current mirror circuit.
Since the potential at the node N3 is changed in this way, the N-type enhancement MIS transistor 2006 constituting the inverter to which the potential of the node N3 is inputted can not be completely turned off in the detection release state, a leak current is generated, resulting in an increase in a consumed electric current.